| 摘要 |
The invention is directed to a bi-quad filter circuit (100) configured with sigma-delta devices (108, 110, 118) that operate as binary rate multipliers (BRMs) (200). Unlike conventional bi-quad filter circuits (100), the invention provides a bi-quad filter (100) configured with a single-bit BRM (200). In another embodiment, the invention further provides a bi-quad filter (100) configured with multiple-bit BRMs.
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