CAPACITOR STRUCTURE AND SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a capacitor structure which can suppress the parasitic capacitance of MOS capacitor. SOLUTION: The MOS capacitor uses an n-type diffusion region 2 formed on the top face of a p-type silicon substrate 1 as a bottom electrode, a gate insulation film 3 formed above the n-type diffusion region 2 as a dielectric layer, and a gate electrode 4 formed on the gate insulation film 3 as a top electrode. The n-type diffusion region 2 is formed at an upper part of a p well 10 formed at the p-type silicon substrate 1. Between the n-type diffusion region 2 and the p well 10, an n--type diffusion region 11 is formed having a lower dopant concentration than that of the n-type diffusion region 2. COPYRIGHT: (C)2006,JPO&NCIPI