Gate structure of semiconductor memory device comprises gate electrode on gate insulation layer, and hard mask formed on gate electrode so that hysteresis area between hard mask and gate electrode layers is specific
摘要
<p>Gate structure of a semiconductor memory device comprises a gate insulation layer (31) formed on a silicon substrate (30); a gate electrode (35) on the gate insulation layer, formed by stacking a polysilicon layer (32) and a metal layer (33); and a hard mask (34) formed on the gate electrode. The hysteresis area between the hard mask and the gate electrode layers is a size ~/ 2x10 120>C dyne/cm 2>. The hard mask includes a material selected from PESiN, PETEOS and PESiN/PETEOS.</p>
