发明名称 INFORMATION PROCESSOR AND MULTI-HIT CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To share a buffer for address conversion (TLB: Translation Lookaside Buffer) among a plurality of threads without generating unnecessary multi-hit in an information processor which operates by a multithread system. SOLUTION: The information processor is provided with the TLB 31 which holds address conversion pairs and thread information, a retrieval part 32 which retrieves an address conversion pair of the same virtual address as a virtual address to be converted into a physical address so as to convert the virtual address into the physical address from the TLB 31, a judgment part 34 which judges, when a plurality of address conversion pairs are retrieved by the retrieval part 32, whether or not two or more pieces of thread information among a plurality of pieces of thread information corresponding to the plurality of address conversion pairs are the same and a multi-hit control part 35 which suppresses output of the multi-hit and executes address conversion when it is judged that the pieces of thread information are different by the judgment part 34. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006040140(A) 申请公布日期 2006.02.09
申请号 JP20040222041 申请日期 2004.07.29
申请人 FUJITSU LTD 发明人 HIRANO TAKAHITO;YAMAZAKI IWAO;HONKURUMADA TSUTOMU
分类号 G06F12/10;G06F9/46 主分类号 G06F12/10
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