发明名称 Enabling verification of a minimal level sensitive timing abstraction model
摘要 A method and a corresponding apparatus for verifying a minimal level sensitive timing abstraction model provides for an extension of the timing abstraction model. The method modifies and runs the timing abstraction model with certain stimulus to establish whether the timing results with the timing abstraction model are identical to the timing result with the modeled circuit. The timing abstraction model extension, which enables verification of the timing abstraction model, only negligibly increases the size of the timing abstraction model, thus keeping STA runtimes short and the memory requirements small.
申请公布号 US6996515(B1) 申请公布日期 2006.02.07
申请号 US20010927204 申请日期 2001.08.10
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 FOLTIN MARTIN;FOUTZ BRIAN;TYLER SEAN
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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