发明名称 |
Integrated circuit memory devices having zig-zag arrangements of column select IO blocks to increase input/output line routing efficiency |
摘要 |
Integrated circuit memory devices include sense amplifier arrays having layouts that are configured to support greater pitch between adjacent input/output lines, while maintaining high levels of integration density. A sense amplifier array is provided having first and second column select I/O blocks that are arranged in an alternating zig-zag layout sequence, with the first column select I/O blocks positioned in a first row of the sense amplifier array and the second column select I/O blocks positioned in a second row of the sense amplifier array. The sense amplifier array also includes an alternating zig-zag layout sequence of first and second N-type (or P-type) sense amplifier blocks that extends back-and-forth between the first and second rows. The zig-zag layout sequence of sense amplifier blocks is interleaved with the zig-zag layout sequence of the column select I/O blocks.
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申请公布号 |
US6996025(B2) |
申请公布日期 |
2006.02.07 |
申请号 |
US20040774902 |
申请日期 |
2004.02.09 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE HYUN-SEOK;KIM KYUNG-HO;KIM HYEUN-SU |
分类号 |
G11C8/00;G11C7/06;G11C7/18;G11C11/4091;G11C11/4097 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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