摘要 |
A clock signal synchronizing device includes a first delay unit with variable delay time connected to an input circuit with a first delay time which receives a first clock signal and outputs a second clock signal. A second delay unit has a fixed delay time portion corresponding to the first delay time, and an additional variable delay time portion. A first phase comparison unit has a first input connected to the output of the input circuit, and a second input connected to the output of the second delay unit. The output signal controls the delay time of the first delay unit. A copy of the input circuit has an input connected to the output of the first delay unit. A second phase comparison unit has an input connected to the output of the copy, and an output signal controls the variable delay time portion of the second delay unit.
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