| 摘要 |
PROBLEM TO BE SOLVED: To provide an instruction execution method using a high-performance RISC-base superscalar processor suitably feasible by a microprocessor. SOLUTION: This microprocessor for fetching an instruction set from an instruction store for interpreting and executing it is provided with an instruction set acquisition means acquiring an instruction set, which is previously decided to be executed and includes an instruction for referring to a register, a data store means storing data in a plurality of registers including a previously decided register 554 and a temporary register 552, and an execution means connected to the instruction set acquisition means for executing the previously decided instruction set sequentially. The execution means gives an instruction so that data processed by an instruction executed outside the sequence are stored in the temporary register, and the register referred by the instruction executed outside the sequence is the previously decided register. COPYRIGHT: (C)2006,JPO&NCIPI
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