| 摘要 |
In a phase-locked loop circuit including a lock detection function, the phase-locked loop circuit includes a lock detection circuit. The lock detection circuit includes a lock-window-entry detection circuit and a lock-detection-signal generation circuit. The lock-window-entry detection circuit detects a front edge of an up signal or a down signal generated by a phase frequency detector at a front edge of a delayed up signal or a delayed down signal to generate a lock-window-entry detection signal, wherein the delayed up signal or the delayed down signal is delayed substantially by as much as a lock window. The lock-detection-signal generation circuit counts an input signal of a phase-locked loop circuit to generate a lock detection signal when the lock-window-entry detection signal is continuously enabled for a predetermined time period. In this manner, a lock detection signal is output only when the phase locking operation has been completed.
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