<p>To match the output frame rates to the input frame rates, a display clock signal is generated that has a frequency locked to the frequency of a reference clock signal. To generate the display clock signal, the period of the vertical incoming data clock is measured using the reference clock signal. The number of pixels disposed in the output frames is subsequently divided by the measured period. A fractional-N phase-locked loop circuit is adapted to multiply the result of the division with the frequency of the reference clock signal to generate the display clock signal. The display clock signal is also locked to the reference clock signal.</p>
申请公布号
WO2006010157(A2)
申请公布日期
2006.01.26
申请号
WO2005US25533
申请日期
2005.07.15
申请人
GREENFOREST CONSULTING, INC.;LOUIE, JAMES YAT;SHYU, MENQ YU