| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To obtain a multigate memory cell having a semiconductor body, and a plurality of gates arranged continuously on the semiconductor body. <P>SOLUTION: Charge storage structure of a semiconductor body is provided with a charge trapping position below a gate among a plurality of gates. A circuit for conducting a source and drain bias voltage to a semiconductor body proximate to first and last continuous gates, and a circuit for conducting a gate bias voltage to the plurality of gates are provided. The multigate memory cell is provided with a continuous multigate channel region below the plurality of continuous gates along with a charge storage position between respective gates. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
