发明名称 Converter circuit with voltage rise rate limitation
摘要 <p>A converter circuit has a DC voltage circuit (1) formed by two series-connected capacitors and a first (5) current rise limiting network (5) connected to a first main terminal (2) and a second current rise limiting network (10) with an inductance (11) and a resistance (12) connected to the second main terminal (3). A first voltage limiting network (15) is connected in parallel to a series circuit of the first and second power semiconductor switches (S1,S2) and to a diode of the first current limiting network (5). A second voltage limiting network (16) is connected in parallel to the series circuit of the third and fourth power semiconductor switches (S3,S4) and to the diode (14) of the second current limiting network (10).</p>
申请公布号 EP1619785(A2) 申请公布日期 2006.01.25
申请号 EP20050405380 申请日期 2005.06.13
申请人 ABB SCHWEIZ AG 发明人 OEDEGARD, BJOERN;APELDOORN, OSCAR
分类号 H02M7/487 主分类号 H02M7/487
代理机构 代理人
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