发明名称 Circuit and method for reducing SRAM standby power
摘要 A method of operating a memory circuit to reduce standby current is disclosed. The method includes applying a first voltage (Vdd) to a power terminal ( 224 ) of a memory cell having a first ( 612 ) and a second ( 614 ) data terminal. A data bit is stored in a memory cell ( 600,602,604,606 ). A second voltage (VDA) different from the first voltage is applied to the power terminal. A third voltage (Ground) is applied to the first and second data terminals. The first voltage is applied to the power terminal.
申请公布号 US6990035(B2) 申请公布日期 2006.01.24
申请号 US20030727888 申请日期 2003.12.03
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 REDWINE DONALD J.;DOERING ROBERT R.
分类号 G11C7/00;G11C11/417 主分类号 G11C7/00
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