发明名称 |
Analog unidirectional serial link architecture |
摘要 |
The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.
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申请公布号 |
US2006008042(A1) |
申请公布日期 |
2006.01.12 |
申请号 |
US20050225600 |
申请日期 |
2005.09.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CRANFORD HAYDEN C.JR.;GARVIN STACY J.;NORMAN VERNON R.;OWCZARSKI PAUL A.;SCHMATZ MARTIN L.;STEVENS JOSEPH M. |
分类号 |
H03D3/24;H03L7/099;H04L7/00;H04L7/033 |
主分类号 |
H03D3/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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