| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic simulator capable of facilitating debugging at the time of lacing occurrence. SOLUTION: The logic simulator 10 simulates operation of a logic circuit model described by a hardware description language (HDL) and is provided with an HDL processing part 100 for creating data necessary for execution of simulation from the hardware description language and a simulation executing part 110 for executing simulation by using the data. The simulation executing part 110 counts the number of delta cycles for performing substitution processing with delta delay at an identical simulation time of day. COPYRIGHT: (C)2006,JPO&NCIPI
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