| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve software error resistance without remarkable increment of cell area and cost as a complete CMOS type SRAM cell. <P>SOLUTION: The gate electrode of a first (second) MISFET for drive and load is formed of an integrated n-type polysilicon in separation from the gate electrode of a first (second) MISFET for transfer, and a first (second) resistance element is formed through control of impurity concentration within the n-type polysilicon. First and second resistance elements are respectively formed in the side of direction opposed to that of the first or second MISFET for drive in front of the gate of the first or second MISFET for load. A wiring from an output node of a second (first) inverter is connected to a contact electrode formed at the upper part of the n-type polysilicon as the first (second) resistance element. The first and second MISFETs for load have the n-type gate electrodes. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
