| 摘要 |
A system for operation verification of a semiconductor integrated circuit has a central processing unit, a design layout memory unit which stores therein design layout information including the design layout configuration of the semiconductor integrated circuit in which a plurality of semiconductor elements are integrated, and a predicted final layout memory unit which stores therein a predicted final layout configuration that has been predicted by the central processing unit by adding an optical proximity effect to the design layout configuration. The system further has a netlister which describes a procedure for causing the central processing unit to produce, as a net list described based on the predicted final layout configuration, a plurality of net lists in which different physical values are registered for a common element in the predicted final layout configuration, a netlist memory unit which stores therein the plurality of net lists, and a circuit simulator which describes a procedure for causing the central processing unit to perform operation verification of the semiconductor integrated circuit by using an arbitrary one of the plurality of net lists.
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