发明名称 |
Boundary synchronization mechanism for a processor of a systolic array |
摘要 |
A mechanism synchronizes instruction code executing on a processor of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a boundary (temporal) synchronization mechanism for cycle-based synchronization within a processor of the array. The synchronization mechanism is generally implemented using specialized synchronization micro operation codes ("opcodes").
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申请公布号 |
US6986022(B1) |
申请公布日期 |
2006.01.10 |
申请号 |
US20010978640 |
申请日期 |
2001.10.16 |
申请人 |
CISCO TECHNOLOGY, INC. |
发明人 |
MARSHALL JOHN WILLIAM;BURNS BARRY S.;KERR DARREN |
分类号 |
G06F15/80 |
主分类号 |
G06F15/80 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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