发明名称 |
Register controlled delay locked loop and its control method |
摘要 |
A register controlled delay locked loop (DLL), including: a coarse delay line for generating a delayed input clock signal by delaying an external clock signal; a fine delay line unit for receiving the delayed input clock signal in order to generate a first fine delayed clock signal and a second fine delayed clock signal; a phase detector for comparing phases of the external clock signal and a feed-backed clock signal in order to generate a phase detection signal based on the comparison result; a phase mixer for generating a mixed clock signal by mixing phases of the first fine delayed clock signal and the second fine delayed clock signal based on a weight value; and a mixer controller for generating the weight value based on the phase detection signal.
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申请公布号 |
US2006001465(A1) |
申请公布日期 |
2006.01.05 |
申请号 |
US20040020597 |
申请日期 |
2004.12.21 |
申请人 |
KWAK JONG-TAE;LEE HYUN-WOO |
发明人 |
KWAK JONG-TAE;LEE HYUN-WOO |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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