| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve deviation between a clock signal and a data signal in a receiving device without sending the clock signal from a transmitting device to the receiving device. <P>SOLUTION: A phase adjusting circuit 303 delays the clock signal clk to adjust the phase and outputs the adjusted clock signal iclk. A flip-flop 305 detects the position relation between a clock signal pdclk generated from the data signal it and the clock signal iclk and outputs a control signal down. A shift register circuit 302 generates a control signal increasing or decreasing delay according to a timing signal sclk generated from the data signal it and outputs it to the phase adjusting circuit 303. A flip-flop 308 latches a data signal dtffin according to the clock signal iclk. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
