| 摘要 |
PROBLEM TO BE SOLVED: To provide a counter circuit having no error even if an operation is initiated at a random timing and capable of reducing power consumption. SOLUTION: If an operation control signal EN is provided, a frequency dividing clock generator 10 outputs a clock signal CK1 having the same frequency as that of a reference clock signal CK and clock signals CK2-CK5 obtained by frequency-dividing the signal CK1 into 1/2, 1/4 and so forth. An operation clock selector 20 selects a clock signal subjected to 1/2<SP>j</SP>frequency division as an operation clock signal CLK when low order j bits of an initial value LD is 0, and supplies the selected signal to a counter 30. In the counter 30 of binary n bits, the count operation of the low order j bits as 0 is stopped according to the initial value LD, and a count operation of high n-j bits is performed in accordance with the operation clock signal CLK. Then, an overflow signal OVF is outputted when the count value overflows. COPYRIGHT: (C)2006,JPO&NCIPI
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