| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To efficiently control the loading/sensing of a setting value to a processor core in a processor such as a CMP having a multicore and so on. <P>SOLUTION: A processor such as a CMP processor having a multicore composition and so on is provided with a core selection flag register, which holds the state of each core, controls output from a processor common block to a core block according to a state of the core selection flag register. By providing a flexible setting method of the core, shortening of system boot time is shortened when a multicore is operated, debug is conducted flexibly, or a yield in the production of semiconductors is improved by saving partially good core chips. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
