<p>A method and apparatus of allowing processors of different speeds to be used in a multi-processor system are disclosed. The method and apparatus comprise a programmable array logic (PAL) or field programmable gate array (FPGA) that detects each of the processors maximum speed and selects a speed common to all of the processors as the operating speed of the processors. The method and apparatus also adjust the system clock to match the speed of the processors.
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申请公布号
EP0848318(A3)
申请公布日期
2006.01.04
申请号
EP19970309790
申请日期
1997.12.04
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
ARROYO, RONALD XAVIER ARROYO;PHAM, KHUONG HUU PHAM