发明名称 Digital delay-locked loop circuits with hierarchical delay adjustment
摘要 Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.
申请公布号 US6982578(B2) 申请公布日期 2006.01.03
申请号 US20030722959 申请日期 2003.11.26
申请人 MICRON TECHNOLOGY, INC. 发明人 LEE SEONG-HOON
分类号 H03L7/06;H03L7/081 主分类号 H03L7/06
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