发明名称 |
Processing and verifying retimed sequential elements in a circuit design |
摘要 |
Provided are a method, system, and program for processing and verifying circuit designs. A circuit design specification written in a hardware definition language is received and zero delay black box code is added to the circuit design specification to position the zero delay black boxes at sequential elements. A synthesis of the circuit design specification is performed to generate a retimed implementation of the circuit design specification. The black boxes are processed in the retimed implementation to verify the synthesis of the circuit design.
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申请公布号 |
US2005289498(A1) |
申请公布日期 |
2005.12.29 |
申请号 |
US20040879781 |
申请日期 |
2004.06.28 |
申请人 |
INTEL CORPORATION |
发明人 |
SAWKAR PRASHANT S.;IYER BALA K.;GOLDENBERG SILVIAN;SAXENA PRASHANT |
分类号 |
G06F9/45;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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