| 摘要 |
A built-in self-test architecture for multiple memories in a chip is proposes in the present invention. In this architecture, a memory testing circuit includes a data generator for generating expected-value data, registers connected in parallel to a plurality of memories respectively so as to be able to transfer, in parallel, memory-readout data from the plurality of memories. The comparators to compare the outputs of registers and the expected-value data with respect to each of the plurality of registers, an identification circuit for identifying the comparator which has detected a disagreement among the plurality of comparators, a readout register which stores the memory-readout data read out from the memory from which the disagreement has been detected and memory-identification information for identifying the memory. The architecture also has an output register which serially reads out the memory-readout data in which the disagreement has been detected and the memory-identification information.
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