发明名称 |
I/O circuitry shared between processor and programmable logic portions of an integrated circuit |
摘要 |
The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins. The data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by a control signal that determines when particular I/O pins are accessed by the programmable logic portion and the embedded processor portion. Control signals that configure the associated I/O pin circuitry to the correct I/O standard are also multiplexed by the shared I/O circuitry of the present invention. Signals received at the shared I/O pins that are transmitted to the embedded processor portion may be concurrently sent to snoop circuitry within the programmable logic portion.
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申请公布号 |
US6980024(B1) |
申请公布日期 |
2005.12.27 |
申请号 |
US20040936878 |
申请日期 |
2004.09.08 |
申请人 |
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发明人 |
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分类号 |
G06F15/78;(IPC1-7):H03K19/017 |
主分类号 |
G06F15/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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