| 摘要 |
A semiconductor memory device disclosed herein has a memory cell array in which memory cells are arranged in a matrix form, data being written into each of the memory cells by passing a cell current therethrough; word lines which are provided in parallel along a row direction in the memory cell array; bit lines which are provided in parallel along a column direction in the memory cell array, the column direction being crossed with the row direction; sense amplifiers which are respectively connected to the bit lines and which write data held in the sense amplifiers into the memory cells; a data line which supplies data to be written into the sense amplifiers; and a control circuit which, in a continuous write operation of performing write operations by continuously switching a column address to select a column, opens only a connection between the sense amplifier selected by the column address and the bit line to write the data held in the sense amplifier into the memory cell.
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