| 摘要 |
In a circuit in which a signal arrival time with respect to a register is different in accordance with the change of a delay time of the circuit, a mechanism capable of adjusting a clock signal of the register is previously provided to deal with the case in which a set-up time in the register is not satisfied due to an increase of the delay time, and the delay time of the clock signal is changed in response to the change of the delay time of the circuit in respective modes. Thereby, the set-up time of data in the register can be satisfied, and an operation frequency of the circuit can be prevented from lowering.
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