发明名称 Data reading structure
摘要 A data reading structure for a 8-bit microprocessor to read several bytes of data at a time has a memory module and a selector module. The memory module has a first memory having a first and second data output ports and a second memory has a third and fourth data output ports. The selector module has a first data selector, a second data selector and a third data selector. The first, second and third data selectors respectively select one output from the first, second, third and fourth data output ports. Thereby, the microprocessor is allowed to read successively three bytes of data from an output terminal of the selector module during a memory read cycle to reduce the fetch time of an instruction.
申请公布号 US2005283581(A1) 申请公布日期 2005.12.22
申请号 US20040868214 申请日期 2004.06.16
申请人 CHIANG CHEN M 发明人 CHIANG CHEN M.
分类号 G06F9/38;G06F12/00;(IPC1-7):G06F12/00 主分类号 G06F9/38
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