发明名称 Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization
摘要 A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous stream of memory is disclosed. A preferred embodiment identifies groups of isomorphic statements within a loop body where the isomorphic statements operate over a contiguous stream of memory over the iteration of the loop. Those identified statements are then converted in to virtual-length vector operations. Next, the hardware's available vector length is used to determine a number of virtual-length vectors to aggregate into a single vector operation for each iteration of the loop. Finally, the aggregated, vectorized loop code is converted into SIMD operations.
申请公布号 US2005283775(A1) 申请公布日期 2005.12.22
申请号 US20040919115 申请日期 2004.08.16
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 EICHENBERGER ALEXANDRE E.;WANG KAI-TING A.;WU PENG
分类号 G06F9/45;(IPC1-7):G06F9/45 主分类号 G06F9/45
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