发明名称 Method and apparatus for performing cache segment flush and cache segment invalidation operations
摘要 A method and apparatus for including in a computer system, instructions for performing cache memory invalidate and cache memory flush operations. In one embodiment, the computer system comprises a cache memory having a plurality of cache lines each of which stores data, and a storage area to store a data operand. An execution unit is coupled to the storage area, and operates on data elements in the data operand to invalidate data in a predetermined portion of the plurality of cache lines in response to receiving a single instruction.
申请公布号 US6978357(B1) 申请公布日期 2005.12.20
申请号 US19980122349 申请日期 1998.07.24
申请人 INTEL CORPORATION 发明人 HACKING LANCE;THAKKAR SHREEKANT;HUFF THOMAS;PENTKOVSKI VLADIMIR;HSIEH HSIEN-CHENG E.
分类号 G06F12/08;(IPC1-7):G06F12/08 主分类号 G06F12/08
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