发明名称 A BUS BUFFER CIRCUIT INCLUDING LOGIC CIRCUIT
摘要 A bus buffer has a controller to generate several control signals; a first terminal via which a first-directional signal is input whereas a second-directional signal is output; a second terminal via which the first-directional signal is output whereas the second-directional signal is input; a first-directional signal processor, provided between the first and second terminals, having a first internal circuit and a first output buffer; a second-directional signal processor, provided between the second and first terminals, having a second internal circuit and a second output buffer; a first input buffer having a first input holder to disactivate the first internal circuit and the first output buffer by using at least one of the control signals; and a second input buffer having a second input holder to disactivate the second internal circuit and the second output buffer by using the at least one control signal, for holding the input to the input buffers at a certain level to decrease a current to pass these circuits, thus achieving low power consumption.
申请公布号 KR100537476(B1) 申请公布日期 2005.12.19
申请号 KR20030013785 申请日期 2003.03.05
申请人 发明人
分类号 G11C7/10;(IPC1-7):G11C7/10 主分类号 G11C7/10
代理机构 代理人
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