发明名称 SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To relieve the marginal defective cell of one bit generated in a plurality of memory cells for one unit by using an ECC circuit without using a redundancy circuit. SOLUTION: In a memory provided with the ECC circuit 15 for performing the error detection and correction of read data by using parity data and the redundancy circuit, the memory cell of one row where the marginal defective cell of a bit number uncorrectable in the ECC circuit 15 occurs is replaced by using the redundancy circuit, and the error correction is performed by using the ECC circuit 15 for the marginal defective cell of the bit number correctable in the ECC circuit 15. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005346822(A) 申请公布日期 2005.12.15
申请号 JP20040164802 申请日期 2004.06.02
申请人 TOSHIBA MICROELECTRONICS CORP;TOSHIBA CORP 发明人 FUKUDA KENJI
分类号 G11C29/42;G11C29/00;(IPC1-7):G11C29/00 主分类号 G11C29/42
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