| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce the influence of the off-leak current of a transistor without increasing power consumption. <P>SOLUTION: Voltage transfer switches 221 and 222 and voltage input / output circuits 231 and 232 are provided on a complementary bus line pair BUS and NBUS so as to be shared by a plurality of columns of a memory cell array 200, and after a complementary bit line pair BITO and NBITO is precharged to a prescribed voltage, the voltage of a normal bit line BITO and the voltage of an inverted bit line NBITO are exchanged before one of all memory cells 201 and 202 belonging to the same column is selected by a word line. Thus, even when the total sum of the off-leak current of an access transistor in the entire memory cells 201 and 202 belonging to the same column is as large as the on-current (drive current) of one drive transistor, the potential difference of a required size is secured between the complementary bit line pair BITO and NBITO at the time of the activation of a sense amplifier 250. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
