| 摘要 |
PROBLEM TO BE SOLVED: To provide a transistor which has a structure having a high flexibility in a design regarding a gate wiring even when an element region where a source diffused layer and a drain diffused layer are alternately formed is increased in an area, and can preferably suppress the reduction of a surge resistance caused by a charge variation (unbalance) of each gate in the same region. SOLUTION: An element region EA is zoned in a lattice shape, and also to each region zoned in the lattice shape, a source cell SC forming the source diffused layer and a drain cell DC forming the drain diffused layer are allocated with regard to a column and a row of the same lattice alternately, respectively. Here, inside the element region EA, a region CA where neither a diffused layer of the source diffused layer nor the drain diffused layer is formed is provided as a contact region of a gate electrode layer composed of polycrystal silicon and a gate wiring EG composed of aluminium. COPYRIGHT: (C)2006,JPO&NCIPI
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