SEMICONDUCTOR DEVICE

摘要

For example, a plurality of diffusion layers (L) are arranged in parallel with bit lines (BL). Gates (G) are arranged such that they intersect with the bit liens (BL) between the diffusion layers (L). A bit line contact (BC) and a source node contact (SC) are alternately arranged for each of a plurality of diffusion layers (L) arranged along the bit lines (BL). A phase change element is disposed on the source node contact (SC). In this way, a single memory cell (MC) is composed of two memory cell transistors (Q1,Q2) and a single phase change element. The phase change element may be disposed not on the source node contact (SC) but on the bit line contact (BC). This can realize, for example, an improvement of driving performance of the memory cell transistors, a reduced area thereof and so on.