| 摘要 |
A downlink frame processing system ( 200 ) includes a packet switch ( 608 ) routing self addressed uplink data ( 706 ) from an input port to an output port, a memory ( 804 ) coupled to the output port, and a downlink scheduler ( 802 ) coupled to the memory ( 804 ). The memory ( 804 ) includes storage for at least two downlink beam hop locations ( 302, 304 ). The downlink scheduler ( 802 ) processes from one of a plurality of segments at least one scheduling entry ( 1312 ) that includes, for example, a header field ( 1316 ) defining at least one of a payload and frame type ( 1404 ) for at least one of a payload and frame ( 1200 ) to be transmitted, and payload data pointers ( 1502, 1504, 1506 ) into the memory ( 804 ).
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