| 摘要 |
PROBLEM TO BE SOLVED: To reduce power consumption and chip area when three sets of binary logics are outputted while being converted into three-valued three differential logics. SOLUTION: A first binary logic signal is inputted to the base of Q411 and an inverted signal is inputted to the base of Q412. A second binary logic signal is inputted to the base of Q416 and an inverted signal is inputted to the base of Q415. A third binary logic signal is inputted to the base of Q413 and an inverted signal is inputted to the base of Q414. Collectors of the Q411 and Q416 are connected with a resistor R417 and a first output is taken out. Collectors of the Q412 and Q413 are connected with a resistor R413 and a second output is taken out. Collectors of the Q414 and Q415 are connected with a resistor R415 and a third output is taken out. Intermediate voltage of a three-valued signal can be outputted without being divided by a resistor. Since three-valued three differential logic signals are outputted as three signals, each transmission line requires only one buffering transistor. COPYRIGHT: (C)2006,JPO&NCIPI
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