发明名称 TESTING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a testing technique to examine wafer in the middle of a metal diffusion process, and a testing method for a semiconductor IC capable of changing the layers of pads to be connected in testing and those of pads to be used when all the production processes are completed for the purpose of preventing reliability degradation caused by pad cracks. <P>SOLUTION: When wafer test is performed for a product of n layers at the stage of m layers, where m is smaller than or equal to n, pads of m layers are provided when probing is performed at the stage of m layers. Furthermore, when wafer test is performed when n-layer diffusion is completed, pads of n layers are provided for probing at the stage of n layers. The m-layer pads and n-layer pads are not electrically connected in a pad region. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005333158(A) 申请公布日期 2005.12.02
申请号 JP20050209888 申请日期 2005.07.20
申请人 NEC ELECTRONICS CORP 发明人 NAKAJIMA KAZUHIRO;KANBA KOJI
分类号 G01R31/28;H01L21/66;H01L21/822;H01L27/04 主分类号 G01R31/28
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