| 摘要 |
PROBLEM TO BE SOLVED: To provide a trigger signal generating circuit which is operable at high speed for generating a frequency-divided clock having a duty ratio of 50%. SOLUTION: 1st to Pth (P is an integer) sub-counters (SC1-SCP) provided in parallel and capable of counting M clocks are included, respectively and 1st to Pth clocks (IC1-ICP) having the same cycle as a reference clock and shifting their phases sequentially for 1/P cycle of the reference clock are supplied to each of the sub-counters. When an N-th (N is an arbitrary value from 1 to P) sub-counter, in the 1st to Pth sub-counters, completely counts the predetermined M clocks, the other sub-counters are initialized all or at least an (N+1)th sub-counter is initialized. After initialization, the (N+1)th sub-counter counts M (N+1)th clocks whose phase is delayed from the Nth clock just for the 1/P clock cycle and when M clocks are completely counted, the next sub-counter is initialized. COPYRIGHT: (C)2006,JPO&NCIPI
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