发明名称 |
Semiconductor device and fabrication method therefor |
摘要 |
A high withstand voltage well is formed on a surface of a semiconductor substrate. A drain region and a source region of a high withstand voltage transistor included in an input protection circuit are formed on the high withstand voltage well. A p-type impurity region is formed adjacent to the lower portion of the drain region of the high withstand voltage transistor. The p-type impurity region is fabricated in the same fabrication step as a low withstand voltage well formed in a region on which a low withstand voltage transistor is formed.
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申请公布号 |
US2005263843(A1) |
申请公布日期 |
2005.12.01 |
申请号 |
US20050137639 |
申请日期 |
2005.05.26 |
申请人 |
RENESAS TECHNOLOGY CORP. |
发明人 |
SAKAKIBARA KIYOHIKO |
分类号 |
H01L21/336;H01L21/8238;H01L27/092;H01L29/00;(IPC1-7):H01L29/00 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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