| 摘要 |
In one illustrative embodiment, the method involves forming a ring oscillator that includes a first grating structure comprised of a plurality of gate electrode structures for a plurality of N-channel transistors and a second grating structure comprised of a plurality of gate electrode structures for a plurality of P-channel transistors, and measuring the critical dimension and/or profile of at least one of the gate electrode structures in the first grating structure and/or the second grating structure using a scatterometry tool. In another embodiment, the method further involves forming at least one capacitance loading structure, comprised of a plurality of features, as a portion of the ring oscillator, and measuring the critical dimension and/or profile of at least one of the features of the capacitance loading structure using a scatterometry tool. |
