| 摘要 |
PROBLEM TO BE SOLVED: To provide an apparatus and a method for designing a semiconductor integrated circuit for decreasing signal delay variations of a logic circuit connected in common to virtual power lines. SOLUTION: There are provided a logic circuit 63 comprised of a transistor of a low gate threshold voltage, a first power line side virtual power line 4 and a second power line side virtual power line 6 for driving the logic circuit 63, a first switch cell 64 comprised of a transistor of a high gate threshold voltage for connecting the first power line side virtual power line 4 and a first power line (GND), and a second switch cell 65 comprised of a transistor of a high gate threshold voltage for connecting the second power line side virtual power line 6 and a second power line (Vdd). A time constant of resistant capacity is kept constant between the first power line side virtual power line 4 and the first power line (GND). COPYRIGHT: (C)2006,JPO&NCIPI
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