发明名称 Circuit-level memory and combinational block modeling
摘要 A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup table is limited by an upper bound representing a total number of memory operations that can occur over a given number of clock cycles.
申请公布号 US6968305(B1) 申请公布日期 2005.11.22
申请号 US20000586191 申请日期 2000.06.02
申请人 AVERANT, INC. 发明人 ISLES ADRIAN J.
分类号 G06F17/50;G06G7/62;(IPC1-7):G06F17/50 主分类号 G06F17/50
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