| 摘要 |
<p>A fractional frequency synthesizer includes a circuit which alternately outputs multiple output signals having different respective periods to drive the average period of the output signal to within a predetermined number of phase steps of a desired period. The phase steps are provided by a plurality of phase-shifted reference clock signals, having the same frequency. The average period of the output signal is a fractional multiple of the period of the reference clock signals.</p> |
