发明名称 |
ESD protection circuit with low parasitic capacitance |
摘要 |
An ESD protection circuit includes a silicon controlled rectifier coupled between a circuit pad and ground for bypassing an ESD current from the circuit pad during an ESD event. An MOS transistor, having a source shared with the silicon controlled rectifier, is coupled between the pad and ground for reducing a trigger voltage of the silicon controlled rectifier during the ESD event. The silicon controlled rectifier has a first diode serially connected to a second diode in an opposite direction, between the pad and the shared source of the MOS transistor, for functioning as a bipolar transistor. In a layout view, a first area for placement of the first and second diodes is interposed between at least two separate sets of second areas for placement of the MOS transistor.
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申请公布号 |
US2005254189(A1) |
申请公布日期 |
2005.11.17 |
申请号 |
US20050091131 |
申请日期 |
2005.03.28 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
WU YI-HSUN;LEE JIAN-HSING |
分类号 |
G01R27/02;G11C17/16;G11C17/18;H01L27/02;H01L29/00;H01L29/74;H02H9/00;(IPC1-7):H02H9/00 |
主分类号 |
G01R27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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