发明名称 Methods and apparatus for the hardware implementation of virtual concatenation and link capacity adjustment over SONET/SDH frames
摘要 Methods and apparatus for the hardware implementation of virtual concatenation and link capacity adjustment over SONET/SDH frames include providing a state machine on chip with a SONET/SDH mapper and providing means whereby a plurality of members of a VCG can share the same state machine. The apparatus of the invention preferably includes a time wheel for granting access to the single state machine and memory for storing state information for each of the VCG members. According to the presently preferred embodiment, the invention is implemented on chip with an OC-3 Ethernet mapper. Up to eighty-four VCG members share the same state machine and memory is provided on the chip for maintaining the state information for eighty-four VCG members. Fifteen bits are used to store the state information for each VCG member in low order and seventeen bits are used to store the state information for each VCG member in high order. The presently preferred time wheel runs at 20 MHz.
申请公布号 US6965612(B2) 申请公布日期 2005.11.15
申请号 US20020323442 申请日期 2002.12.18
申请人 TRANSWITCH CORPORATION 发明人 CHOHAN HARPREET S.;ROUAUD CHRISTOPHE
分类号 H04J3/04;H04J3/16;H04Q11/04;(IPC1-7):H04J3/16;H04L12/28 主分类号 H04J3/04
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