| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve soft error resistance without increasing the cell area of an SRAM cell or the manufacture man-hour, and without deteriorating the characteristics of the SRAM cell. <P>SOLUTION: An SRAM cell 1 comprises a pair of inverters employing load PMOS transistors Qp1 and Qp2 having a polysilicon film 5 functioning as a gate electrode and gate interconnect line, and a salicide layer 6 formed thereon. A region 10 where the salicide layer does not exist is provided as a high resistance part at a part of the polysilicon film 5. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
