| 摘要 |
A semiconductor memory device for performing an OCD calibration control operation in order to adjust a data output impedance, including: means for decoding an address signal to generate an OCD default control signal, an OCD operation signal and plural data; means for receiving a plural-bit data to generate an OCD control code; means for receiving the OCD control code and the OCD operation signal to generate a plurality of impedance adjustment control signals; and means for receiving the plural data and adjusting the data output impedance in response to the plurality of impedance adjustment control signals.
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